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PRELIMINARY
CY8C41123 and CY8C41223
Linear Power PSoCTM Devices
1.0 Features
1.1 Key Features
* Extended Operating Voltage of 2.5V to 36V * 2 HV Linear Opamp Control Loops for Driving Power PFETs * 2 HV Analog Sense Inputs * 4KB of Flash * 256 Bytes of SRAM * * * * 2 Comparators with DAC References 6- to 12-Bit ADC (20 Ksps at 8 Bits) Configurable Analog Mux, 10:1 or 5:2 Differential Configurable Digital Blocks -- 8- to 16-Bit Timers and Counters -- Connectable to All GPIO Pins -- Digital Blocks can Drive Outputs to 36V -- Complex Peripherals by Combining Blocks
1.3 1.2 Improved Features
* Very Low Current Mode for 100 nA Sleep (Deep Sleep) * Analog Absolute Accuracy (0.75%) * Additional Flexibility for Sleep Modes
Applications
* Battery Chargers (Linear or Fly Back) * White LED Drivers * Temperature Sensor (Thermistor, Thermocouple)
2.0
Block Diagram
HVdd
LowDrop-Out Regulator
InternalVdd
ANALOG and HIGH VOLTAGE SECTIONS
ODAC0 VDAC0 GDO0 VS0 P0[6] P0[4] P0[2] Temp Vss Vref Vbg
GDO1 VS1 P0[7] P0[5] P0[3] P0[1] P1[1]
ODAC1 VBG VDAC1 VDAC1 IBIAS Analog to Digital Convertor
VDAC0
Atten1 AMuxBus3 AMuxBus1
Atten0 AMuxBus2 AMuxBus0
P0[0] P1[0]
SYSTEM RESOURCES PSoC CORE
SleepandWatchdog POR andLVD COMP1 ACLK COMP0 ACLK LowSpeed Oscillator
ODAC1
ODAC0
Internal Voltage Reference Internal Main Oscillator
M8C CORE PSoCCPU 4KBFlash
256BSRAM
Global Digital InterconnectBus System Bus
I2C DBC00 SystemResets DigitalPSoC BlockArray InterruptController 1 DigitalRow DBC01 DBD02 DBD03 Digital Clocks
DIGITAL SYSTEM
Figure 2-1. Block Diagram
Cypress Semiconductor Corporation Document 001-00360 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134 * 408.943.2600 Revised November 17, 2005
PRELIMINARY
3.0 Complete Feature List 4.0
CY8C41123 and CY8C41223
PSoC Functional Overview
* Extended Operating Voltage of 2.5V to 36V * Powerful Harvard Architecture Processor -- M8C Processor Speeds to 24 MHz -- Low Power at High Speed -- Industrial Temperature Range: -40C to +85C * Additional Flexibility for Sleep Modes -- Select when System Resources are Shut Down -- Very Low Current Mode for 100 nA Sleep (Deep Sleep) * 2 Advanced Power PSoC Blocks -- 2 High Voltage Analog Sense Inputs -- 2 High Voltage Linear Opamp Control Loops for Driving Power PFETs * Advanced Analog Blocks -- Analog Absolute Accuracy (0.75%) -- 2 Comparators with DAC References -- 6- to 12-Bit ADC (20 Ksps at 8 Bits) -- Configurable Analog Mux, 10:1 or 5:2 Differential * 4 Advanced Digital Blocks -- 8- to 16-Bit Timers and Counters -- Connectable to All GPIO Pins -- Complex Peripherals by Combining Blocks * Flexible On-Chip Memory -- 4KB Flash Program Storage 50,000 Erase/Write Cycles -- 256 Bytes SRAM -- In-System Serial Programming (ISSPTM) -- Partial Flash Updates (64-Byte Blocks) -- Flexible Protection Modes -- EEPROM Emulation in Flash * Precision, Programmable Clocking * Complete Development Tools -- Free Development Software (PSoCTM Designer) -- Full-Featured, In-Circuit Emulator and Programmer -- Full Speed Emulation -- Complex Breakpoint Structure -- 128KB Trace Memory -- Free Application Generation Software (PSoC ExpressTM) * Additional System Resources -- I2CTM Master, Slave, and Multi-Master to 400 kHz -- Watchdog and Sleep Timers -- User-Configurable Low Voltage Detection -- Integrated Supervisory Circuit -- On-Chip Precision Voltage Reference -- 4-Bit Current References
The key feature set of the Linear Power PSoC family is the ability to be powered from and connect to voltages above the standard 5V logic voltage used by most microcontrollers. The PSoC's HVdd pin can connect to a supply voltage of up to 36V. Internally, an LDO regulator converts the supply voltage to 5V for powering the analog system, digital system, the core, and the GPIO. High voltage signals can be connected to the analog circuitry through one of two selectable attenuators, each having three ranges. These precision dividers reduce the external analog voltage by a factor of 4, 8, or 16. This allows single-ended or differential signals with up to 36V common mode to be measured with the ADC. The GPIO pins are not high-voltage tolerant. Signals with voltages exceeding VGPIO (as shown in the Absolute Maximum Ratings table, 8.2) cannot be connected to the GPIO pins (P0 [7:0] and P1 [1:0]). Doing so will damage the device. The Linear Power PSoC family consists of several MixedSignal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low-cost single-chip programmable component. A Linear Power PSoC device includes configurable analog, digital, and power blocks, as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture, as illustrated in Figure 2-1, is comprised of five main areas: the Core, the System Resources, the Digital System, the Analog System, and the Power Control System. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each PSoC device includes 4 digital blocks and up to 10 general purpose IO (GPIO). The GPIO provide access to the global digital and analog interconnects.
4.1
Linear Power PSoC Core
The Linear Power PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low-speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as digital clocks for increased flexibility of the PSoC mixed-signal arrays; I2C functionality for implementing master, slave, and multi-master; an internal voltage reference of 1.3V for a number of analog PSoC subsystems; and various system resets supported by the M8C.
3.1
Differences from CY8C42x23
* The CY8C41x23 is a cost-reduced version of the CY8C42x23 and targets linear-control applications. * The HVO pin and current DACs have been eliminated and the PWM with deadband capability has been removed from the digital blocks.
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PRELIMINARY
4.2 Digital System
CY8C41123 and CY8C41223
The Digital System is composed of 4 Basic (Type C) digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32bit peripherals, which are called user module references. A sampling of digital block configurations is listed below. * Counters (8 to 32 bit) * Timers (8 to 32 bit) The digital blocks can be connected to any GPIO through a set of global buses that can route any signal to any pin. The buses also allow signal multiplexing and the combining of signals through logic operations. This configurability frees designs from the constraints of a fixed peripheral controller.
ANALOG and HIGH VOLTAGE SECTIONS
ODAC1 VDAC1 VDAC1 VBG IBIAS Analog to Digital Convertor ODAC0 VDAC0 GDO0 VS0 P0[6] P0[4] P0[2] Temp Vss Vref Vbg Atten1 AMuxBus3 AMuxBus1 Atten0 AMuxBus2 AMuxBus0 P0[0] P1[0]
GDO1 VS1 P0[7] P0[5] P0[3] P0[1] P1[1]
VDAC0
4.3
Multiple Sleep Modes
COMP1 ACLK COMP0 ACLK ODAC1 ODAC0
The CY8C41x23 devices can have some of the system resources (the SleepTimer/Watchdog Timer, the Voltage Regulator or the Power Supply Supervisor) powered down in order to achieve the desired level of sleep current. Sleep modes with current levels from 750 A in idle to 0.1 A in deep sleep, and wakeup times from instantaneous to 400 sec are available. Deeper sleep modes have longer wakeup times and sleep modes with more resource power typically have shorter wakeup times.
Figure 4-1. Analog Block Diagram
4.5
High Voltage Interface
4.4
Analog System
The CY8C41x23 devices have solid analog performance, low (100 V) offsets, reduced temperature sensitivity, and are capable of measuring 0.75% absolute voltage accuracy. The Analog System is composed of configurable blocks to allow creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Following are some of the more common PSoC analog functions (most available as user modules). * Analog-to-digital converters (up to 12-bit resolution with single-ended or differential inputs). * Adjustable input gain of 1/4, 1, 4, or 16 for the ADC. * Pin-to-pin comparator with low power mode for operation during sleep. * Single-ended or differential comparators (up to 2) with absolute (1.3V) reference or internal DAC reference. * 1.3V reference (as a System Resource).
The Gate Drive Outputs (GDO0 and GDO1) can each be used to drive the gate of a high-side PFET in a linear regulator. The GDO0 and GDO1 outputs will drive between HVdd-5V and HVdd. The Gate Drive Outputs are driven by an amplifier and used to control a PFET in a linear mode. A sense voltage can be fed back to the amplifier through an HV attenuator to implement a constant voltage or constant current driver. The output of the VDAC can be used to set the target voltage of the regulator.
4.6
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports P0 and P1. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. This bus is split into four sections, AMux Bus 0 and AMux Bus 2, which connect to the even port pins and AMux Bus 1 and AMux Bus 3, which connect to the odd port pins. The four sections can be combined to support dual-channel single-end processing, single-channel differential processing, or dual-channel differential processing. They can also be connected as one bus that can route to all GPIO pins. Other multiplexer applications include: * Chip-wide mux that allows analog input from up to 10 GPIO pins. * Crosspoint connection between any GPIO pin combinations.
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PRELIMINARY
4.7 Additional System Resources
CY8C41123 and CY8C41223
System Resources, some of which have been previously listed, provide additional capability useful to complete systems implemented in a single power block. Additional resources include an I2C master and slave, low voltage detection, and power on reset. Brief statements describing the merits of each system resource are presented below. * Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. * The I2C module provides 50-, 100-, and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. * Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. * An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
4.8
Development Tools
* Standard Cypress PSoC IDE tools are available for debugging the CY8C41x23 family of parts. However, the additional trace length and a minimal ground plane in the Flexpod can create noise problems that make it difficult to debug a Power PSoC design. A custom bonded On-Chip Debug (OCD) device is available in an 32-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or high analog accuracy requirements. The QFN package is compact and can be connected to the ICE through a high density connector. * In-System Serial Programming (ISSP) is available. However, ISSP for Power PSoC differs from ISSP for standard PSoC devices. With Power PSoC devices, the power pin (HVdd) should not be connected directly to the Vdd pin of the ISSP connector. Doing so can damage the programming device.
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PRELIMINARY
5.0
5.1
CY8C41123 and CY8C41223
Typical Linear Power PSoC Applications
Linear White LED Driver
A white LED driver is a constant current power supply. By driving the same current through a set of LEDs in series, the intensity of the LEDs can be closely matched. The CY8C41x23 Linear Power PSoC can be configured as a constant voltage or constant current linear supply. In this configuration, the HVdd voltage is high enough to drive the LEDs in series and current regulation is needed. White LEDs typically have a forward voltage of around 4V, so in the four LED configuration shown in Figure 5-1, HVdd would have to be around 16V (plus allowance for voltage losses in the FET and the current sense resistor, RISENSE). The HVdd voltage is converted to 5V by the internal Low Drop-Out Regulator for use by the Power PSoC Core. To maintain constant voltage, the gate of the External PFET is controlled by the GDO0 pin and driven in a linear mode. The voltage at the top of the load, connected to VS0, is attenuated by the internal resistive element, Atten0. The voltage out of the attenuator is fed into the positive terminal of an amplifier configured as a voltage follower. The amplifier's negative input is connected to the output of the voltage DAC, VDAC0. This creates a feedback loop that maintains the VS0 node at a voltage proportional to the VDAC0 setting. The Atten0 output is also connected to the ADC so the control software can monitor the output voltage. To maintain constant current, the voltage across the RISENSE resistor is routed through pin P0[4] and AMuxBus0 to the ADC where it is monitored. The control software adjusts the VDAC0 setting, based on current sense measurements, to achieve the desired current through the load. 5.1.1 Resources
This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Linear Power PSoC still has all of its digital resources, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels to the ADC, and over 90% of the CPU available for other tasks.
HVdd HVdd
HVdd LowDrop-Out Regulator Internal Vdd
ANALOG and HIGH VOLTAGE SECTIONS
ODAC0 VDAC0 VDAC0
GDO1 VS1 P0[7] P0[5] P0[3]
ODAC1 VBG VDAC1 VDAC1 IBIAS Analog to Digital Convertor
GDO0 VS0 P0[6] P0[4] P0[2]
Ext. PFET
Temp
P0[1] P1[1]
Vss Vref Vbg
Atten1 AMuxBus3 AMuxBus1
Atten0 AMuxBus2 AMuxBus0
P0[0] P1[0]
COMP1
COMP0
RISENSE
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ACLK
ACLK
ODAC1
ODAC0
Figure 5-1. Linear White LED Driver
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PRELIMINARY
5.2 Linear Battery Charger
CY8C41123 and CY8C41223
A battery charger is constant current and constant voltage power supply. At different points in a charging cycle a Lithium Ion battery requires a constant current or a constant voltage to be applied. The CY8C41x23 Linear Power PSoC can be configured as a constant voltage or constant current linear supply. In this configuration, the HVdd voltage is high enough to drive one or more battery in series. Lithium Ion batteries have a fully charged voltage of 4.2V. With the two-cell configuration in Figure 5-2, HVdd would have to be at least 8.4V (plus allowance for voltage losses in the FET and the current sense resistor, RISENSE). The HVdd voltage is converted to 5V by the internal Low Drop-Out Regulator for use by the Power PSoC Core. To maintain constant voltage, the gate of the External PFET is controlled by the GDO0 pin and driven in a linear mode. The voltage at the top of the load, connected to VS0, is attenuated by the internal resistive element, Atten0. The voltage out of the attenuator is fed into the positive terminal of an amplifier configured as a voltage follower. The amplifier's negative input is connected to the output of the voltage DAC, VDAC0. This creates a feedback loop that maintains the VS0 node at a voltage proportional to the VDAC0 setting. The Atten0 output is also connected to the ADC so the control software can monitor the output voltage. The accuracy of the ADC and the control loop are better than 0.75%. Meeting high accuracy is critical to Lithium Ion batteries. To maintain constant current, the voltage across the RISENSE resistor is routed through pin P0[4] and AMuxBus0 to the ADC where it is monitored. The control software adjusts the VDAC0 setting, based on current sense measurements, to achieve the desired current through the load. The current sense voltage is also connected to the positive input of COMP0. The negative input of COMP0 is controlled by the output of ODAC0. If the current sense voltage exceeds the ODAC0 setting, the output of the comparator will be latched high. This acts as an over-current detection circuit, which can be cleared by the control software. The output of the comparator, COMP0, can be connected to the enable of the GDO0 output driver. This configures the Power PSoC so that an over-current condition will shut off the External PFET. 5.2.1 Resources
This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Linear Power PSoC still has all of its digital resources, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels to the ADC, and over 90% of the CPU available to implement the battery charging algorithm and other tasks.
HVdd HVdd
HVdd LowDrop-Out Regulator Internal Vdd
ANALOG and HIGH VOLTAGE SECTIONS
ODAC0 VDAC0 VDAC0
GDO1 VS1 P0[7] P0[5] P0[3]
ODAC1 VBG VDAC1 VDAC1 IBIAS Analog to Digital Convertor
GDO0 VS0 P0[6] P0[4] P0[2]
Ext. PFET
Temp
P0[1] P1[1]
Vss Vref Vbg
Atten1 AMuxBus3 AMuxBus1
Atten0 AMuxBus2 AMuxBus0
P0[0] P1[0]
COMP1
COMP0
RISENSE
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ACLK
ACLK
ODAC1
ODAC0
Figure 5-2. Linear Battery Charger
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PRELIMINARY
6.0 Pin Assignment
CY8C41123 and CY8C41223
This section lists, describes, and illustrates all Linear Power PSoC device pins and pinout configurations. For up-to-date ordering, pinout, and packaging information, go to http://www.cypress.com/psoc.
6.1
Pinouts
PSoC devices are available in a variety of packages. Refer to the following information for details on individual devices. Every port pin (labeled with a "P") in the following tables and illustrations is capable of digital IO. 6.1.1 8-Pin SOIC Part Pinouts
The 8-pin SOIC part is for the CY8C41123 PSoC device.
8-Pin Part Pinout (SOIC)
Analog Pin No. 1 2 3 4 5 6 7 8 IO IO Power IO IO Power I I HVI Digital
CY8C41123 PSoC Device
Name GD1 P0[1] P1[1] Vss P1[0] P0[0] VS0 HVdd High Voltage Sense 0 Supply Voltage I2C Clock* Ground Connection I2C Data* Description High Side Linear Gate Driver 1
GD1 P0[1] I2C* P1[1] Vss
HVO I I
1 2 SOIC 3 4
8 7 6 5
HV dd VS0 P0[0] P1[0] I2C*
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
6.1.2
16-Pin SOIC Part Pinouts
The 16-pin SOIC part is for the CY8C41223 PSoC device.
16-Pin Part Pinout (SOIC)
Analog Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO IO IO IO IO IO IO IO IO IO Power I I I I I HVI HVO Power Digital
CY8C41223 PSoC Device
Name GD1 VS1 P0[7] P0[5] P0[3] P0[1] P1[1] Vss P1[0] P0[0] P0[2] P0[4] P0[6] VS0 GD0 HVdd High Voltage Sense 0 High Side Linear Gate Driver 0 Supply Voltage Optional External CLK Input (EXTCLK) I2C Clock* Ground Connection I2C Data* Description High Side Linear Gate Driver 1 High Voltage Sense 1 I2C Clock I2C Data
HVO HVI I I I I I
GD1 VS1 SCL, P0[7] SDA, P0[5] P0[3] P0[1] I2C*, P1[1] Vss
1 2 3 4 5 6 7 8
SOIC
16 15 14 13 12 11 10 9
HVdd GD0 VS0 P0[6] P0[4] P0[2], EXTCLK P0[0] P1[0], I2C*
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
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PRELIMINARY
6.1.3 32-Pin QFN Part Pinouts
CY8C41123 and CY8C41223
The 32-pin QFN part is for the CY8C41000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production.
32-Pin OCD Part Pinout (QFN**)
Analog
GD1 HVdd HVdd GD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP Power HVO Power Power HVO HVO HVI HVI HVO IO IO IO IO I OCD OCD I I I I IO IO Power I I OCD OCD IO IO IO IO I I I I
NC NC
No Connection No Connection
NC NC HCLK CCLK P0[7] P0[5] P0[3] P0[1] 1 2 3 4 5 6 7 8
32 31 30 29 28 27
NC VS1
Name
Description
26 25 24 23 22 21 20 19 18 17 NC OCDE OCDO XRES P0[6] P0[4] P0[2] P0[0]
HCLK On-Chip Debug Clock CCLK On-Chip Debug Clock P0[7] P0[5] P0[3] P0[1] NC NC P1[1] Vss P1[0] NC NC NC P0[0] P0[2] P0[4] P0[6] XRES External Reset OCDO On-Chip Debug Data OCDE On-Chip Debug Data NC DNU VS0 GD0 HVdd HVdd GD1 VS1 NC Vss No Connection Do Not Use High Voltage Sense 0 High Side Gate Driver 0 Supply Voltage Supply Voltage High Side Gate Driver 1 High Voltage Sense 1 No Connection Center Pad Must be Connected to Ground Optional External CLK Input (EXTCLK) I2C Data* No Connection No Connection No Connection No Connection No Connection I2C Clock* I2C Clock I2C Data
QFN (T op View) (CP)
Not for Production
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage, NC = No Connection, OCD = On-Chip Debug. * These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details. ** The QFN package has a center pad that must be connected to ground (Vss).
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
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NC NC I2C*, P1[1] Vss I2C*, P1[0] NC NC NC
9 10 11 12 13 14 15 16
VS0 DNU
Pin No.
Digital
CY8C41000 OCD PSoC Device
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PRELIMINARY
7.0 Registers
CY8C41123 and CY8C41223
This section discusses the registers of the Power PSoC device. It lists all the registers in mapping tables, in address order.
7.1
Register Conventions
The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
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PRELIMINARY
7.2
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 HVP2_DR
CY8C41123 and CY8C41223
Register Map Bank 0 Table: User Space
Name Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Access RW RW RW RW RW RW RW RW RW Name 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F R W RW RW R W RW RW R W RW RW R W RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CMP_SYN CMP_LFN0 CMP_LMD CMP_CDS CMP_CIS CMP_RDC CMP_GOEN0 CMP_CLK CMP_CR CMP_SRC CMP_MUX0 CMP_MUX1 AC0_MUX AC0_CR0 AC0_CR1 AC0_CR2 AC0_MSP AC0_LSP AC0_MSR AC0_LSR AC0_CC 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0GF RW RW RW RW RW RW RW RW # VDAC_CR VDAC_DR0 VDAC_DR1 AA_REF PWR0_CR PWR1_CR ASC00CR0 ASC00CR1 ASC00CR2 ASC00CR3 ASC01CR0 ASC01CR1 ASC01CR2 ASC01CR3 Addr (0,Hex) Access Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF CPU_SCR2 CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT RW RW RW RW RW RW RW RW IDAC_D P0_MUX P1_MUX Addr (0,Hex) Access Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RSW # # RL RW # RW # RW RW RW RW RW RW RW RW RC W RW RW RW Access
DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DBD02DR0 DBD02DR1 DBD02DR2 DBD02CR0 DBD03DR0 DBD03DR1 DBD03DR2 DBD03CR0
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Blank fields are Reserved and should not be accessed.
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PRELIMINARY
7.3 Register Map Bank 1 Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 HVP2_DM0 HVP2_DM1 HVP2_DS0 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC01FN DBC01IN DBC01OU DBD02FN DBD02IN DBD02OU DBD03FN DBD03IN DBD03OU 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0GF RDIV0 VDAC_TR VDAC_ITRIP0 BUS_TOP SLP_CR0 SLP_CR1 SLP_CR2 Access Name 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
CY8C41123 and CY8C41223
Addr (1,Hex)
Access
Name
Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6
Access
IDAC_CR
C7 C8 C9 CA CB CC CD CE CF
RW
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU AC0_GOEN
D0 D1 D2 D3 D4 D5 D6 D7
RW RW RW RW RW
AC0_CLK
D8 D9 DA DB DC
RW
OSC_GO_EN OSC_CR4 OSC_CR3 RW RW RW RW OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
DD DE DF E0 E1 E2 E3 E4 E5 E6 E7
RW RW RW RW RW RW RW R
RW RW
IMO_TR LSO_TR BDG_TR
E8 E9 EA EB EC
W RW RW
RW AA_TR
ED EE EF
RW
RW RW RW RW RW RW RW RW CPU_F
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC CPU_SCR2 CPU_SCR1 CPU_SCR0 FD FE FF RSW # # RL
Blank fields are Reserved and should not be accessed.
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PRELIMINARY
8.0 Electrical Specifications
CY8C41123 and CY8C41223
Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted.
8.1
Frequencies
Refer to Table 8.4 for the electrical specifications on the internal main oscillator (IMO) using slow IMO (SLIMO) mode, which is set using the CPU_SCR1 register.
36
36
~ ~
4.75 HVdd Voltage 3.00 2.40 93 kHz 3 MHz CPU Fre que ncy 12 MHz
~ ~
4.75
~ ~
HVdd Voltage
SLIMO Mode=1
SLIMO Mode = 0
SLIMO ~ Mode=0~
Figure 8-1a. Supply Voltage versus CPU Frequency
8.2
Absolute Maximum Ratingsa
Conditions Higher storage temperatures will reduce data retention time. Min. -50 -40 -0.5 -0.5 -0.5 HVdd 5.5 -0.5 -0.5 -25 -50 Typ. - - - - - - - - - - Max. +100 +85 +40 HVdd + 0.5 5.5 HVdd + 0.5 HVdd + 0.5 HVdd + 0.5 +50 +50 Units oC
oC
Parameter Description TSTG Storage Temperature TA HVdd VGPIO VGPIO36 VGD VVS VHVO IMIO IMIOHV
Ambient Temperature with Power Applied Supply Voltage on HVdd Relative to Vss DC Input to any Low Voltage HVdd 5.0V. Input Pin DC Input to any Low Voltage HVdd > 5.0V. Input Pin DC Input to any Gate Drive Pin DC Input to High Voltage Sense Pin DC Applied to High Voltage Outputs in High-Z State Maximum Current into any Low Voltage Port Pin Maximum Current into any High Voltage Port Pin
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l i d ng Va a t i n r pe io O Re g
24 MHz
3.60
3.00
2.40 93 kHz
SLIMO Mode=1 SLIMO Mode=1
6 MHz IM O Fre que ncy 12 MHz
SLIMO Mode=0
24 MHz
Figure 8-1b. IMO Frequency Trim Options
V V V V
mA mA
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PRELIMINARY
8.2 Absolute Maximum Ratingsa (continued)
Maximum Current into any Gate Drive Pin Electro Static Discharge Voltage Human Body Model ESD. Electro Static Discharge to High Human Body Model ESD. Voltage Port Pin Latch-up Current
CY8C41123 and CY8C41223
IMIOGDb ESD ESDHV LU
-10 2000 2000 -
- - - -
10 - - 200
mA V V mA
a. Operation at these conditions degrades reliability. b. Cannot result in pin voltage exceeding VGD limits or thermal specifications being exceeded.
8.3
Operating Temperature
Conditions The temperature rise from ambient to junction is package specific. See "Thermal Impedances per Package" on page 32. The system designer must limit the power consumption to comply with this requirement. Min. -40 -40 Typ. - - Max. +85 +100 Units oC oC
Parameter Description TA Ambient Temperature TJ Junction Temperature
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.4
DC Chip-Level Specifications
Conditions See DC POR and LVD specifications table 8.14 on page 20. Conditions are HVdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Conditions are HVdd = 36V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Conditions are HVdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. Min. 2.5 - Typ. - 3 Max. 36 4 Units V mA
Parameter Description HVdd Supply Voltage IDD Supply Current, IMO = 24 MHz
IDD36
Supply Current, IMO = 24 MHz
-
3
4
mA
IDD3
Supply Current, IMO = 6 MHz
-
1.2
2
mA
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PRELIMINARY
8.4
IDD27
CY8C41123 and CY8C41223
DC Chip-Level Specifications (continued)
Supply Current, IMO = 6 MHz Conditions are HVdd = 2.7V, TA = 25 oC, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. SLIMO mode = 1. IMO = 6 MHz. Conditions are HVdd = 5.0V, -40 oC TA 85 oC. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC TA 85 oC, analog power = off. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC TA 85 oC, analog power = off. Conditions are with internal slow speed oscillator, HVdd = 3.3V, -40 oC TA 85 oC, analog power = off. Conditions are with internal slow speed oscillator, HVdd = 3.3V, TA = 25 oC, analog power = off. Conditions are bypass mode on, deep sleep enabled, HVdd = 3.3V, TA = 25 oC, analog power = off. Conditions are analog power off, deep sleep enabled, HVdd = 6V, TA = 25 oC. Trimmed for HVdd > 3.0V. Trimmed for HVdd = 2.5V to 3.0V. - 1.1 1.5 mA
IRESET ISBI
Supply Current while Reset Supply Current in Idle Mode
- -
- -
250 750
A A A A
ISB
ISBR
ISBW
ISBD
ISBDHV
VREF VREF27
Supervised Sleep Current (POR, LVD, SleepTimer, WDT, and Voltage Regulation) Regulated Sleep Current (No POR, No LVD, but with SleepTimer, WDT, and Voltage Regulation) Watchdog Sleep Current (No POR, No LVD, No SleepTimer, No Voltage Regulation but with WDT) Deep Sleep Current (No POR, No LVD, No SleepTimer, No Voltage Regulation and No WDT Deep Sleep Current at HV (No POR, No LVD, No SleepTimer, No Voltage Regulation and No WDT Reference Voltage (Bandgap) Reference Voltage (Bandgap)
-
2.8
3
-
-
1
-
0.5
-
A
-
0.1
-
A
-
((HVdd - 6) / 2) + 0.1
-
A
1.291 1.16
1.30 1.30
1.309 1.33
V V
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PRELIMINARY
CY8C41123 and CY8C41223
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.5
4.75V to 36V DC GPIO Specifications
Conditions Min. 4 4 3.6 Typ. 5.6 5.6 - Max. 8 8 5.4 Units k k V
Parameter Description RPU Pull-up Resistor RPD Pull-down Resistor VOHa High Output Level
VOLa
Low Output Level
VIL VIH VH IIL CIN COUT IOHb
Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 A. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC. Current Supplied while 4.5V VOH 5.5V, Maintaining 10% Regulation HVdd = 4.75V to 36V.
IOH = 10 mA, HVdd = 4.75V to 36V maximum 40 mA on even port pins (for example, P0[2], P1[0]), maximum 40 mA on odd port pins (for example, P0[3], P1[1]). IOL = 25 mA, HVdd = 4.75V to 36V maximum 90 mA on even port pins (for example, P0[2], P1[0]), maximum 90 mA on odd port pins (for example, P0[3], P1[1]). HVdd = 4.75V to 36V. HVdd = 4.75V to 36V.
-
-
0.75
V
- 2.1 - - - - 5.5
- - 60 1 3.5 3.5 -
0.8 - - - 10 10 -
V V mV nA pF pF mA
a. IOH and IOL are also limited by the die temperature. See "Thermal Considerations" on page 31. b. Odd and even port pins are regulated separately, therefore the current limit total applies separately to all odd port pins and to all even port pins.
8.6
3.0V to 5.0V DC GPIO Specifications
Conditions Min. 4 4 HVdd 1.0 Typ. 5.6 5.6 - Max. 8 8 HVdd Units k k V
Parameter Description RPU Pull-up Resistor RPD Pull-down Resistor VOHa High Output Level
VOLa
Low Output Level
VIL VIH
Input Low Level Input High Level
IOH = 8 mA, HVdd = 3.0V to 3.6V maximum 30 mA on even port pins (for example, P0[2], P1[0]), maximum 30 mA on odd port pins (for example, P0[3], P1[1]). IOL = 16 mA, HVdd = 3.0V to 3.6V maximum 60 mA on even port pins (for example, P0[2], P1[0]), maximum 60 mA on odd port pins (for example, P0[3], P1[1]). HVdd = 3.0V to 3.6V. HVdd = 3.0V to 3.6V.
-
-
0.75
V
- 2.1
- -
0.8 -
V V
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PRELIMINARY
8.6
VH IIL CIN COUT
CY8C41123 and CY8C41223
3.0V to 5.0V DC GPIO Specifications (continued)
Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 A. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC. - - - - 60 1 3.5 3.5 - - 10 10 mV nA pF pF
a. IOH and IOL are also limited by the die temperature. See "Thermal Considerations" on page 31.
8.7
2.5V to 3.0V DC GPIO Specifications
Conditions Min. 4 4 HVdd 1.0 Typ. 5.6 5.6 - Max. 8 8 HVdd Units k k V
Parameter Description Pull-up Resistor RPU RPD Pull-down Resistor a VOH High Output Level
VOLa
Low Output Level
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Gross tested to 1 A. Capacitive Load on Pins as Input Package and pin dependent. Temp = 25oC. Capacitive Load on Pins as Package and pin dependent. Temp = Output 25oC.
IOH = 2 mA, HVdd = 2.5V to 3.0V maximum 16 mA on even port pins (for example, P0[2], P1[0]), maximum 16 mA on odd port pins (for example, P0[3], P1[1]). IOL = 8 mA, HVdd = 2.5V to 3.0V maximum 40 mA on even port pins (for example, P0[2], P1[0]), maximum 40 mA on odd port pins (for example, P0[3], P1[1]). HVdd = 2.5V to 3.0V. HVdd = 2.5V to 3.0V.
-
-
0.75
V
- 2.0 - - - -
- - 60 1 3.5 3.5
0.8 - - - 10 10
V V mV nA pF pF
a. IOH and IOL are also limited by the die temperature. See "Thermal Considerations" on page 31.
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.8
DC Comparator Specifications
Conditions Min. - Typ. - Max. 100 Units V
Parameter Description VOSSYN Input Offset Voltage in Synchronous Mode (Absolute Value) Input Offset Voltage in NonVOS Synchronous Mode (Absolute Value) Current Consumption in ICOMPSYN Synchronous Mode Current Consumption of ICOMP Comparator ICOMPLP Current Consumption in Low Power Mode VIN27 Input Voltage Range VIN36 Input Voltage Range VINLP27 Input Voltage Range in Low Power Mode VINLP36 Input Voltage Range in Low Power Mode
-
2.5
15
mV
- HVdd = 2.5V to 36V. HVdd = 2.5V to 36V. HVdd = 2.5V to 5V. HVdd = 5V to 36V. HVdd = 2.5V to 5V. HVdd = 5V to 36V. - - 0 0 0 0
100 10 3 - - - -
200 30 10 HVdd 5.0 HVdd -1.1 3.9
A A A V V V V
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.9
DC Analog-to-Digital Converter Specifications
Description Conditions Input Offset Voltage Input Voltage Range Voltage on Analog Mux Bus. High Voltage Sense Input Range Voltage on Analog Mux Bus. Input Impedance Resolution INL Error DNL Error Absolute System Errora Factory trimmed at ADC gains of 1/4, 1, 4, 16. Min. - 0 0 - 6 - - - Typ. - - - 100K - - - - Max. 100 3 HVdd - 12 1 1/2 0.75% Units V V V bits LSb LSb
Parameter VOS VIN HVIN RIN INL DNL
a. Maximum error is 11% for HVdd = 2.5V to 3.0V; consistent with VREF27 specifications.
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.10 DC Linear Control Specifications
Parameter VOS RATIO1 RATIO2 RATIO3 RATTEN Description Conditions Comparator Input Offset Voltage Attenuation Resistor Ratioa Attenuation Resistor Ratioa Attenuation Resistor Ratioa Attenuator Resistance Control Loop Reference Full range is 0V to VREF. Resolution Loop Control Reference Settinga Pre-Programmed Over-Current Set Point Pre-Programmed Over-Current Set Point Pre-Programmed Over-Current With VDAC_CR Mode = 1. Set Point Pre-Programmed Over-Current With VDAC_CR Mode = 1. Set Point Min. - - - - - - 0 120 240 360 720 Typ. - 4 8 16 400K 8 - 150 300 450 900 Max. 100 - - - - - VREF 180 360 540 1080 Units V
bits V mV mV mV mV
VDAC VOC1 VOC2 VOC3 VOC4
a. Error in this parameter is included in the Absolute System Error.
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PRELIMINARY
CY8C41123 and CY8C41223
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.11
4.75V to 36V DC Linear Gate Drivea
Conditions HVdd = 5V to 36V. HVdd = 5V to 36V. Min. HVdd 0.1 - Typ. - HVdd - 5 Max. - - Units V V
Parameter Description VOHGD High Output Voltage VOLGD Low Output Voltage
a. To maintain the Absolute System Error per table 8.9, the current into or out of the Gate Drive Output must be less than 100 nA.
8.12 2.5V to 5V DC Linear Gate Drive
Parameter Description VOHGD High Output Voltage VOLGD Low Output Voltage Conditions IOH = 100 nA, HVdd = 2.5V to 5V. IOL = 100 nA, HVdd = 2.5V to 5V. Min. HVdd 0.1 - Typ. - - Max. - 1.0 Units V V
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.13 DC Analog Mux Bus Specifications
Parameter Description RSW Switch Resistance to Common Analog Bus Conditions HVdd 5V. HVdd = 3.3V. HVdd = 2.7V. Min. - - - Typ. 1000 1500 2000 Max. - - - Units
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the temperature range: -40C TA 85C. Typical parameters apply at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the Power PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register.
8.14 DC POR and LVD Specifications
Parameter VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Conditions Vdd must be greater than or equal to 2.6V during startup, reset from the XRES pin, or reset from Watchdog. Min. - - - 2.50 2.85 2.95 3.06 4.37 4.50 4.62 4.71 Typ. 2.46 2.82 4.55 2.550 2.920 3.02 3.13 4.48 4.64 4.73 4.81 Max. 2.50 2.95 4.70 2.61a 2.99b 3.09 3.20 4.55 4.75 4.83 4.95 Units V V V V V V V V V V V
a. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. b. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.15 DC Programming Specifications
Parameter Description VddIWRITE Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Level During Programming or Verify VIHP Input High Level During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Level During Programming or Verify VOHV Output High Level During Programming or Verify VOHV36 Output High Level During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)a FlashDR Flash Data Retention Conditions Min. 2.80 - - 2.1 Driving internal pull-down resistor. - Typ. - 5 - - - Max. - 25 0.8 - 0.2 Units V mA V V mA
Driving internal pull-down resistor.
-
-
1.5
mA
- HVdd = 2.5V to 5V. HVdd = 5V to 36V. Erase/write cycles per block. Erase/write cycles. HVdd 1.0 3.6 50 1,800 10
- - 5.0 - - -
0.75 HVdd - - - -
V V V KCycles KCycles Years
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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PRELIMINARY
CY8C41123 and CY8C41223
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.16 3.0V to 36V AC Chip-Level Specifications
Parameter Description FIMO24 Internal Main Oscillator Frequency for 24 MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz Conditions Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8-1b on page 12. SLIMO mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See Figure 8-1b on page 12. SLIMO mode = 1. Min. 23.4 Typ. 24 Max. 24.6a,b,c 6.15a,b,c 24.6a,b 12.3b,c 49.2a,b,d 24.6b,d 1.5 60 - 49.2a,c - 600 12.3 - 0 30 30 400 3 Units MHz
5.85
6
MHz
CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Refer to the AC Digital Block Specifications. F24M Digital PSoC Block Frequency F1K Internal Low Speed Oscillator Frequency DC24M 24 MHz Duty Cycle Step24M 24 MHz Trim Step Size Fout48M 48 MHz Output Frequency Trimmed. Utilizing factory trim values. Jitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared FMAX Maximum Frequency of Signal on Row Input or Row Output TRAMP Supply Ramp Time TSBI Wakeup Time from Idle Mode TSB Wakeup Time from Supervised Sleep TSBR Wakeup Time from Regulated Sleep TSBW Wakeup Time from Watchdog Sleep TSBD Wakeup Time from Deep Sleep
FCPU1 FCPU2 F48M
0.91 0.91 0 0 0.6 40 - 46.8 - - - 0 - - - - -
24 12 48 24 1 50 50 48.0 300 - - - - - - - -
MHz MHz MHz MHz kHz % kHz MHz ps ps MHz s s s s s ms
a. b. c. d.
4.75V < HVdd < 36V, -40C TA 70C. Accuracy derived from Internal Main Oscillator with appropriate trim for HVdd range. 3.0V < HVdd < 3.6V, -40C TA 70C. See the individual user module data sheets for information on maximum frequencies for user modules.
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PRELIMINARY
CY8C41123 and CY8C41223
8.17 2.5V to 3.0V AC Chip-Level Specifications
Parameter Description FIMO12 Internal Main Oscillator Frequency for 12 MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz Conditions Trimmed for 2.7V operation using factory trim values. See Figure 8-1b on page 12. SLIMO mode = 0. Trimmed for 2.7V operation using factory trim values. See Figure 8-1b on page 12. SLIMO mode = 1. Min. 11.5 Typ. 12 Max. 12.5a,b 6.24a,b 3.12a 12.5a,b 1.5 60 - 600 12.5 - Units MHz
5.76
6
MHz
CPU Frequency (2.7V Nominal) Digital PSoC Block Frequency Refer to the AC Digital Block Speci(2.7V Nominal) fications. F1K Internal Low Speed Oscillator Frequency DC12M 12 MHz Duty Cycle Jitter12M1P 12 MHz Period Jitter (IMO) Peak-to-Peak Jitter12M1R 12 MHz Period Jitter (IMO) Root Mean Squared FMAX Maximum Frequency of Signal on Row Input or Row Output TRAMP Supply Ramp Time
FCPU1 FBLK27
0.90 0 0.6 40 - - - 0
3 12 1 50 340 - - -
MHz MHz kHz % ps ps MHz s
a. Accuracy derived from Internal Main Oscillator with appropriate trim for HVdd range. b. See the individual user module data sheets for information on maximum frequencies for user modules.
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.18 3.0V and 36V AC GPIO Specifications
Parameter Description FGPIO GPIO Operating Frequency TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF TFallS Fall Time, Slow Strong Mode, Cload = 50 pF Conditions Normal Strong Mode. HVdd = 4.5 to 5.25V, 10% - 90%. HVdd = 4.5 to 5.25V, 10% - 90%. HVdd = 3 to 5.25V, 10% - 90%. HVdd = 3 to 5.25V, 10% - 90%. Min. 0 3 2 10 10 Typ. - - - 27 22 Max. 12.5 18 18 - - Units MHz ns ns ns ns
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PRELIMINARY
CY8C41123 and CY8C41223
8.19 2.5V to 3.0V AC GPIO Specifications
Parameter Description FGPIO GPIO Operating Frequency TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF TFallS Fall Time, Slow Strong Mode, Cload = 50 pF Conditions Normal Strong Mode. HVdd = 2.5 to 3.0V, 10% - 90%. HVdd = 2.5 to 3.0V, 10% - 90%. HVdd = 2.5 to 3.0V, 10% - 90%. HVdd = 2.5 to 3.0V, 10% - 90%. Min. 0 6 6 18 18 Typ. - - - 40 40 Max. 3.12 50 50 120 120 Units MHz ns ns ns ns
90% GPIO Pin Output Voltage 10%
TRiseF TRiseS
TFallF TFallS
Figure 8-2. GPIO Timing Diagram
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.20 AC Comparator Specifications
Parameter Description TRSYNC27 Response Time in Synchronous Mode (50 mV Overdrive) TRSYNC36 Response Time in Synchronous Mode (50 mV Overdrive) TR27 Response Time (50 mV Overdrive) TR36 Response Time (50 mV Overdrive) TRLP27 Response Time in Low Power TRLP36 Response Time in Low Power Conditions HVdd = 2.5V to 3.0V. Output clocked at 12 MHz. HVdd = 3.0V to 36V. Output clocked at 24 MHz. HVdd = 2.5V to 3.0V. HVdd = 3.0V to 36V. HVdd = 2.5V to 3.0V HVdd = 3.0V to 36V Min. - - - - - - Typ. 84 42 - - - - Max. - - 200 100 400 200 Units ns ns ns ns ns ns
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CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.21 AC Analog-to-Digital Converter Specifications
Parameter Description Sample Ratea, b 8-Bit Sample Rateb Conditions 12 bits to 6 bits at 6 MHz. Min. 1.46 - Typ. - 23.4 Max. 93.75 - Units Ksps Ksps
a. Dependent on clock frequency and bit resolution. See individual user module data sheets. b. For HVdd = 2.5V to 3.0V, sample rates are halved. Bit BPEN in the AC0_CLK register must be set to 1.
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.22 3.0V to 36V AC Digital Block Specifications
Parameter Description Timer Capture Pulse Width Maximum Frequency (Capture Not Used) Maximum Frequency (With or Without Capture) Counter Enable Pulse Width Maximum Frequency (Enable Not Used) Maximum Frequency (With or Without Enable Input) Conditions 4.75V < HVdd < 36V. 3.0V < HVdd < 36V. Min. 50a - - 50a - - Typ. - - - - - - Max. - 49.9 25.0 - 49.9 25.0 Units ns MHz MHz ns MHz MHz
4.75V < HVdd < 36V. 3.0V < HVdd < 36V.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
8.23 2.5V to 3.0V AC Digital Block Specifications
Parameter Description Timer Capture Pulse Width Maximum Frequency Counter Enable Pulse Width Maximum Frequency Conditions Min. 100a - 100a - Typ. - - - - Max. - 12.5 - 12.5 Units ns MHz ns MHz
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
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CY8C41123 and CY8C41223
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.24 4.75V to 36V AC Linear Gate Drive
Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Conditions Min. 0.8 Typ. - Max. - Units MHz
8.25 3.0V to 5.0V AC Linear Gate Drive
Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Conditions Min. 0.7 200 Typ. - - Max. - - Units MHz kHz
8.26 2.5V to 3.0V AC Linear Gate Drive
Parameter Description BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Conditions Min. 0.6 180 Typ. - - Max. - - Units MHz kHz
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CY8C41123 and CY8C41223
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.27 4.75V to 36V AC External Clock Specifications
Parameter FOSCEXT - - - Description Frequency High Period Low Period Power Up IMO to Switch Conditions Min. 0.090 20.6 20.6 150 Typ. - - - - Max. 25.0 5300 - - Units MHz ns ns s
8.28 3.0V to 5.0V AC External Clock Specifications
Parameter Description FOSCEXT Frequency with CPU Clock divide by 1a FOSCEXT Frequency with CPU Clock divide by 2 or greaterb - High Period with CPU Clock divide by 1 - Low Period with CPU Clock divide by 1 - Power Up IMO to Switch Conditions Min. 0.090 0.180 41.7 41.7 150 Typ. - - - - - Max. 12.5 25.0 5300 - - Units MHz MHz ns ns s
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
8.29 2.5V to 3.0V AC External Clock Specifications
Parameter Description FOSCEXT Frequency with CPU Clock divide by 1a Frequency with CPU Clock FOSCEXT divide by 4 or greaterb - High Period with CPU Clock divide by 1 - Low Period with CPU Clock divide by 1 - Power Up IMO to Switch Conditions Min. 0.090 0.180 41.7 41.7 150 Typ. - - - - - Max. 3.12 12.5 5300 - - Units MHz MHz ns ns s
a. Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 4 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.30 AC Programming Specifications
Parameter Description Conditions TRSCLK Rise Time of SCLK TFSCLK Fall Time of SCLK TSSCLK Data Set up Time to Falling Edge of SCLK THSCLK Data Hold Time from Falling Edge of SCLK FSCLK Frequency of SCLK TERASEB Flash Erase Time (Block) TWRITE Flash Block Write Time TDSCLK Data Out Delay from Falling HVdd > 3.6 Edge of SCLK TDSCLK3 Data Out Delay from Falling 3.0 HVdd 3.6 Edge of SCLK TDSCLK2 Data Out Delay from Falling 2.5 HVdd 3.0 Edge of SCLK Min. 1 1 40 40 0 - - - - - Typ. - - - - - 20 20 - - - Max. 20 20 - - 8 - - 45 50 70 Units ns ns ns ns MHz ms ms ns ns ns
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.31 3.0V to 36V AC Characteristics of I2C SDA and SCL Pins
Parameter Description SCL Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock TLOWI2C THIGHI2C HIGH Period of the SCL Clock Set-up Time for a Repeated TSUSTAI2C START Condition THDDATI2C Data Hold Time TSUDATI2C Data Set-up Time TSUSTOI2C Set-up Time for STOP Condition TBUFI2C Bus Free Time Between a STOP and START Condition Pulse Width of spikes are TSPI2C suppressed by the input filter. Conditions Standard Mode Min. Max. 0 100 4.0 - Fast Mode Min. Max. 0 400 0.6 - Units kHz s s s s s ns s s ns
4.7 4.0 4.7 0 250 4.0 4.7 -
- - - - - - - -
1.3 0.6 0.6 0 100a 0.6 1.3 0
- - - - - - - 50
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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PRELIMINARY
CY8C41123 and CY8C41223
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 36V and -40C TA 85C (referred to as 5V operation), 3.0V to 3.6V and -40C TA 85C (referred to as 3.3V operation), or 2.5V to 3.0V and -40C TA 85C (referred to as 2.7V operation), respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only.
8.32 2.5V to 3.0V AC Characteristics of I2C SDA and SCL Pins (Fast Mode not Supported)
Parameter Description SCL Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock TLOWI2C THIGHI2C HIGH Period of the SCL Clock Set-up Time for a Repeated TSUSTAI2C START Condition THDDATI2C Data Hold Time TSUDATI2C Data Set-up Time TSUSTOI2C Set-up Time for STOP Condition TBUFI2C Bus Free Time Between a STOP and START Condition Conditions Standard Mode Min. Max. 0 100 4.0 - Units kHz s s s s s ns s s
4.7 4.0 4.7 0 250 4.0 4.7
- - - - - - -
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S
Figure 8-3. Definition for Timing for Fast/Standard Mode on the I2C Bus
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PRELIMINARY
9.0 Thermal Considerations
CY8C41123 and CY8C41223
However, HVdd - VOH can be quite large and current sourced by GPIO must be looked at carefully when using HVdd voltages greater than 5V. The equation for GPIO power dissipation is shown in Equation 3, where ISink is the total current being sunk by GPIO pins, and ISource is the total current being sourced by GPIO pins. PGPIO = VOL * ISink + (HVdd - VOH) * ISource Equation 3
The Linear Power PSoC device can support a supply voltage up to 36V. An internal linear regulator provides the nominal 5 volts used to power the M8C processor and other internal resources. Because regulating to a lower voltage generates excess heat, care must be taken to not exceed the maximum junction temperature of the PSoC device when using higher supply voltages. The junction temperature depends on the ambient temperature, the amount of power being dissipated in the device and the thermal resistance (JA) of the package. In Linear Power PSoC devices, dissipated power can be broken into four sources: the PSoC core (CPU, PSoC blocks and system resources), the General Purpose Inputs/Outputs (GPIO), and the Gate Drive outputs (GD). The equation for junction temperature is shown in Equation 1, where JA is the thermal resistance of the device package. TJ = TA + JA * (PCore + PGPIO + PGD) Equation 1
The power dissipated by the high voltage Gate Drives (GD0 and GD1) is divided into a current sink and current source element. With the GD pins, the (HVdd - VOHGD) component is relatively small and the VOLGD component can be large (approximately HVdd - 5V). Therefore, with the GD pins, care must be taken to consider the effects of sinking currents. The equation for GD power dissipation is shown in Equation 4, where ISinkGD is the total current sunk by the GD pins, and ISourceGD is the total current sourced by the GD pins. PGD = VOLGD * ISinkGD + (HVdd - VOHGD) * ISourceGD
The core power dissipated in the PSoC is the supply voltage (HVdd) times the combined current of: the CPU, digital blocks, analog blocks and system resources (Idd). The equation for the PSoC core power dissipation is: PCore = HVdd * Idd Equation 2 The power dissipated in the PSoC due to the GPIO can be divided into two elements: current being sourced and current being sunk. Because VOL is a relatively small value (less than 1V), the sinking current will not be a major contributor to heat in the Linear Power PSoC.
Equation 4 The following figures show the effects of supply voltage and current on the temperature of the PSoC. Figure 9-1a shows the maximum current with a varied supply voltage at an ambient temperature of 70C and Figure 9-1b shows the maximum current with a varied supply voltage at an ambient temperature of 85C. The PSoC model used assumes Idd = 5mA and all other current is sourced by GPIO. Each curve in the figures shows the maximum ISource that can be tolerated (TJ remains below the maximum limit) at various supply voltages between 2.5V and 36V, for a specific package. The maximum current is clipped at 85 mA due to drive limitations on the GPIO pins. The package types available with Linear Power PSoC devices are shown. Thermal resistance (JA) for the packages can be found in Section 9.1 on page 32.
90 80 70
90 80 70
Idd + IGPIO
Idd + IGPIO
60 50
60 50 40
16-pin SOIC
40 30 20
16-pin SOIC
30 20
8-pin SOIC
1 0 0 0 1 0 20
8-pin SOIC
1 0 0
HVdd
30
0
1 0
20
HVdd
30
Figure 9-1a. Maximum Current vs. Supply Voltage by Package (70o Ambient) Document 001-00360 Rev. *A
Figure 9-1b. Maximum Current vs. Supply Voltage by Package (85o Ambient) Page 31 of 36
PRELIMINARY
CY8C41123 and CY8C41223
9.1
Thermal Impedances per Package
Package 8 SOIC 16 SOIC 32 QFN Typical JA * 186oC/W 124oC/W 22oC/W
* Thermal resistance from silicon junction to ambient (TJ = TA + POWER x JA).
9.2
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Package 8 SOIC 16 SOIC 32 QFN Minimum Peak Temperature* 240oC 240oC 240oC Maximum Peak Temperature 260oC 260oC 260oC
* Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
10.0 CY8C41x23 PSoC Device Key Features and Ordering Information
The following table lists the CY8C41x23 Power PSoC device's key package features and ordering codes . Temperature Range XRES Pin
No No No No Yes
Digital IO Pins
4 4 10 10 10
Package
Ordering Code
8-Pin SOIC 8-Pin SOIC Tape and Reel 16-Pin SOIC 16-Pin SOIC Tape and Reel 32-Pin OCD QFN*
CY8C41123-24SXI CY8C41123-24SXIT CY8C41223-24SXI CY8C41223-24SXIT CY8C41000-24LFXI*
4K 4K 4K 4K 4K
256 256 256 256 256
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
2 2 2 2 2
4 4 4 4 4
2 2 2 2 2
* This part is only used for in-circuit debugging. It is NOT available for production.
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HV GPO
0 0 0 0 0
Analog Channel
Flash (Bytes)
SRAM (Bytes)
Power Blocks
Digital Blocks
PRELIMINARY
11.0 Package Diagrams
CY8C41123 and CY8C41223
51-85066-*C
Figure 11-1. 8-Lead (150) SOIC
PIN 1 ID
8
1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
Figure 11-2. 16-Lead (150) SOIC
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CY8C41123 and CY8C41223
E-PAD X, Y for this product is 3.71 mm, 3.71 mm (+/-0.08 mm)
51-85188 *A
Figure 11-3. 32-Lead (5x5 mm) QFN Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
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PRELIMINARY
CY8C41123 and CY8C41223
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134 Phone: 408.943.2600 Web Sites: Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm
Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation and "Programmable Systemon-Chip," PSoC, PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
CY8C41123 and CY8C41223
Description Title: CY8C41123 and CY8C41223 Linear Power PSoCTM Devices Document Number: 001-00360 REV. ** *A ECN NO. 391186 406572 Issue Date See ECN See ECN Orig. of Change HMT HMT Description of Change New data sheet. Preliminary for PR3. Add RATTEN to the DC Linear Control Specifications table. Add CY corporate address on Information page. Implement CY standard QFN package terminology.
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